IET計(jì)算機(jī)和數(shù)字技術(shù)出版技術(shù)論文，描述了電子和嵌入式系統(tǒng)芯片上數(shù)字系統(tǒng)設(shè)計(jì)和測試各個(gè)方面的最新研究和開發(fā)工作，包括設(shè)計(jì)自動(dòng)化工具（方法、算法和體系結(jié)構(gòu)）的開發(fā)。基于縮小CMOS技術(shù)相關(guān)問題的論文尤其受歡迎。它面向計(jì)算機(jī)和數(shù)字系統(tǒng)設(shè)計(jì)和測試領(lǐng)域的研究人員、工程師和教育工作者。重點(diǎn)關(guān)注的主題領(lǐng)域有：設(shè)計(jì)方法和工具：CAD/EDA工具、硬件描述語言、高級和體系結(jié)構(gòu)綜合、硬件/軟件協(xié)同設(shè)計(jì)、基于平臺(tái)的設(shè)計(jì)、3D堆疊和電路設(shè)計(jì)、系統(tǒng)芯片架構(gòu)和IP核心、嵌入式系統(tǒng)、邏輯綜合、低功耗設(shè)計(jì)和功率優(yōu)化。仿真、測試和驗(yàn)證：電氣和定時(shí)仿真、基于仿真的驗(yàn)證、硬件/軟件協(xié)同仿真和驗(yàn)證、混合域技術(shù)建模和仿真、硅后驗(yàn)證、功率分析和估計(jì)、互連建模和信號完整性分析、硬件信任和安全、可測試性設(shè)計(jì)、嵌入式核心測試、系統(tǒng)芯片測試、在線測試、自動(dòng)測試生成和延遲測試、低功率測試、可靠性、故障建模和容錯(cuò)。處理器和系統(tǒng)架構(gòu)：許多核心系統(tǒng)、通用和特定于應(yīng)用程序的處理器、DSP應(yīng)用程序的計(jì)算算法、算術(shù)和邏輯單元、緩存存儲(chǔ)器、內(nèi)存管理、協(xié)處理器和加速器、芯片上的系統(tǒng)和網(wǎng)絡(luò)、嵌入式核心、平臺(tái)、多處理器、分布式系統(tǒng)、通信協(xié)議和低功耗問題。可配置計(jì)算：嵌入式核心、FPGA、快速原型、自適應(yīng)計(jì)算、可演化和靜態(tài)、動(dòng)態(tài)可重構(gòu)和可重編程系統(tǒng)、可重構(gòu)硬件。變率、功率和老化設(shè)計(jì)：變率、功率和老化感知設(shè)計(jì)、存儲(chǔ)器、FPGA、IP組件、3D疊加、能量采集的設(shè)計(jì)方法。案例研究：新興應(yīng)用、工業(yè)設(shè)計(jì)應(yīng)用和設(shè)計(jì)框架。

IET Computers and Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.The key subject areas of interest are:Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.Case Studies: emerging applications, applications in industrial designs, and design frameworks.